FIG. 1 illustrates an example of a NPN bipolar transistor. The transistor illustrated in FIG. 1 includes a contact 1. The contact 1 may be made of a semiconductor material, such as polycrystalline silicon.
The contact 1 is formed over a region of a substrate 3 at a location where an emitter 5 of the transistor has been formed. A layer 7 of a dielectric material may be arranged on the substrate between the emitter 5 and the contact 1. Often, the dielectric material of the layer 7 is an oxide.
Below emitter 5 lies the base region 9 of the transistor. Below region 9 lies collector 11. FIG. 1 also illustrates the doping and flow of current within an NPN bipolar transistor.
Under normal bias conditions, or forward active mode, the emitter-base (E-B) junction is forward biased, 5 and 9 in FIG. 1, and the collector base junction, 11 and 9 in FIG. 1. is reversed biased. Electrons are ejected from the emitter into the base. Then, the electrons diffuse across the base region where they are swept across the reverse biased C-B junction into the collector. The collector current IC is associated with the flows of electrons from the emitter. On the other hand, the base current IB is a function of the holes ejected from the base region. The holes can either recombine in the single crystal emitter or flow into the polysilicon emitter region 1, which is usually highly doped polycrystalline silicon.
The current again, beta (β), may be described by the relationship between the collector current and base current.
Beta is defined as (collector current)/(base current). In other words, beta equals IC/IB. Generally, the desired value of beta is 100.
Resistance created by dielectric material of region 7 may affect the base current, as shown in FIG. 2. Along these lines, as the resistance created by the region between the contact 1 and the emitter 5 increases, base current decreases and, thus, beta increases. In contrast, if the resistance of region 7 is low, the resulting base current is high and, thus, beta is low.
Controlling the dielectric thickness in region 7 for a bipolar transistor typically is critical to controlling the current gain, beta.
Typically, two processes have been used for depositing polycrystalline (polysilicon) on the emitter Si in the past. According to the first process, a horizontal CVD polysilicon deposition tube has been used extensively. The polysilicon is deposited on the single crystalline Si emitter after the single crystalline Si has been precleaned. In this case, dielectric region 7 may be thin since the only oxidation that occurs in region 7 in the transistor illustrated in FIGS. 1 and 2 is that which occurs as the wafers enter the horizontal CVD tube. In this case, residual oxygen trapped in the system when the wafers are loaded may react with the emitter Si at insert temperatures of approximately 625° C. It has been found that very little oxidation of the emitter Si occurs in this instance. The resulting polysilicon is deposited on a Si surface with essentially native oxide.
Region 7 in this case has a very low resistance and, thus, Beta is low at approximately 50–60. Because the interfacial oxidation is essentially uncontrolled, Beta is found to be highly variable from lot to lot using the horizontal polysilicon deposition process.
In the second type of known process used, the polysilicon layer over the emitter may be deposited using a vertical chemical vapor deposition (CVD) polysilicon deposition tube in which the Si region of the emitter may be oxidized in situ, typically after an initial wet preclean. In this case, a batch of wafers may be loaded into the furnace, the chamber evacuated and then a mixture of an inert gas and oxygen may be leaked into the chamber at temperatures of approximately 600° C. In this case, Beta can be set to 100.
However, different technologies of Bipolar transistors typically require different levels of interfacial oxide and, thus, need to be run separately. Also, variation of the level of oxidation across a batch of wafers can occur. In addition, the typical cost issues associated with batch versus single wafer processing are encountered.